`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    14:36:34 11/15/2024 
// Design Name: 
// Module Name:    Main 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Main(A,B,C0,F,C4
    );

	input [3:0]A;
	input [3:0]B;
	input C0;
	
	output [3:0]F;
	output C4;
	
	wire [4:1]C;
	Over_Adder OA1(A,B,C0,C);
	
	wire [3:0]G;
	
	FullAdder add1(A0,B0,C0,F0,G0);
	FullAdder add2(A1,B1,C1,F1,G1);
	FullAdder add3(A2,B2,C2,F2,G2);
	FullAdder add4(A3,B3,C3,F3,G3);
	

	

endmodule
